1. Field of the Invention
The present invention generally relates to a wiring substrate, a method for manufacturing the wiring substrate, and a semiconductor package including the wiring substrate.
2. Description of the Related Art
There is known a semiconductor package having a semiconductor chip mounted on a wiring substrate via solder bumps or the like. In this semiconductor package, the wiring substrate acts as an interposer during a process of connecting the semiconductor chip to a target substrate (e.g., motherboard). A related art example of a semiconductor package 500 having a wiring substrate 100 acting as an interposer is described with reference to FIG. 1.
FIG. 1 is a cross-sectional view of the semiconductor package 500 according to the related art example. With reference to FIG. 1, the semiconductor package 500 has a semiconductor chip 200 mounted on a substantially center portion of the wiring substrate 100 via plural semiconductor bumps 300. The semiconductor chip 200 is sealed to the wiring substrate 100 with an underfill resin.
The wiring substrate 100 has a layered structure in which a solder resist layer 160, a third wiring layer 130, a second insulating layer 150, a second wiring layer 120, a first insulating layer 140, and a first wiring layer 110 are layered in this order. The first wiring layer 110 and the second wiring layer 120 are electrically connected via first via holes 140x provided inside the first insulating layer 140. The second wiring layer 120 and the third wiring layer 130 are electrically connected via second via holes 150x provided inside the second insulating layer 150.
An outer connection terminal (e.g., solder ball) 170 is formed on the third wiring layer 13 being exposed at a corresponding opening part 160x of the solder resist layer 160. The first wiring layer 110 functions as an electrode pad to be connected to a corresponding electrode pad 220 of the semiconductor chip 200. The outer connection terminal 170 functions as a terminal to be connected to a target substrate (e.g., motherboard). The wiring substrate 100 is typically formed of plural layers due to constraints such as wiring width or via hole diameter.
The semiconductor chip 200 includes a semiconductor substrate 210 and the electrode pad 220 formed on the semiconductor substrate 210. The semiconductor substrate 210 is formed of a substrate (e.g., silicon substrate) having a semiconductor integrated circuit (not illustrated) formed thereon. The electrode pad 220, which is formed on one side of the semiconductor substrate 210, is electrically connected to the semiconductor integrated circuit (not illustrated).
The first wiring layer 110 of the wiring substrate 100 is electrically connected to a corresponding electrode pad 220 of the semiconductor chip 200 via a corresponding solder bump 300. The underfill resin 400 is filled at an interface space between the semiconductor chip 200 and the wiring substrate 100.
Next, a method of manufacturing a semiconductor package according to a related art example is described. In FIGS. 2, 3A and 3B, like components are denoted by like reference numerals as of those of FIG. 1 and are not further explained.
The wiring substrate 100 and the semiconductor chip 200, which are manufactured by known methods, are prepared as illustrated in FIG. 2. Plural pre-solder bumps 410 are formed on the first wiring layer 110 of the wiring substrate 100. Plural pre-solder bumps 420 are formed on corresponding electrode pads 220 of the semiconductor chip 200.
Then, as illustrated in FIG. 3A, the first wiring layer 110 side of the wiring substrate 100 and the electrode pad 220 side of the semiconductor chip 200 are faced against each other in a manner that the positions of the pre-solder bumps 410 match the positions of the pre-solder bumps 420. Then, as illustrated in FIG. 3B, the solder bumps 300 are formed by melting the pre-solder bumps 410, 420 with a heating temperature of, for example, 230° C.
Further, in FIG. 3B, by filling the interface space between the semiconductor chip 200 and the wiring substrate 100, the manufacturing of the semiconductor package 500 mounted with the semiconductor chip 200 (the same as the semiconductor chip illustrated in FIG. 1) is completed. The wiring substrate 100 is to be formed having a thickness to some degree for preventing the wiring substrate 100 from being bent by cure shrinkage of the underfill resin 400.
The semiconductor package 500 is to be connected to a target substrate (e.g., motherboard) via the outer connection terminals 170. Thereby, with the above-described semiconductor package 500, the wiring substrate 100 functions as an interposer for connecting the semiconductor chip 200 and the target substrate (e.g., motherboard).
In the evolution of downsizing, due to advances in the refining (fine size) of the semiconductor chip, the interposer used for mounting the semiconductor chip is also desired to have refined (fine-sized) wiring. However, it is becoming difficult to satisfy such desire with the wiring substrate illustrated in FIG. 1. Although consideration is being made for a Si (silicon) based multilayer interposer that satisfies the desire for forming fine-sized wiring, a large investment is to be made on the facility for manufacturing the multilayer interposer. This leads to an increase of manufacturing cost.